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general description the ds2775?s2778 report available capacity forrechargeable lithium-ion (li+) and li+ polymer (li-poly) batteries in mah and as a percentage of full. safe oper- ation is ensured by the integrated li+ protector. the ds2776/ds2778 support sha-1-based challenge- response authentication in addition to all other ds2775/ ds2777 features. precision measurements of voltage, temperature, and current, along with a cell characteristics table and application parameters, are used for capacity estima- tion calculations. the capacity registers report a con- servative estimate of the amount of charge that can be removed given the current temperature, discharge rate, stored charge, and application parameters. the ds2775?s2778 operate from +4.0v to +9.2v for direct integration into battery packs with two li+ or li- poly cells. in addition to nonvolatile storage for cell compensation and application parameters, the ds2775?s2778 offer 16 bytes of eeprom for use by the host system and/or pack manufacturer to store battery lot and date tracking information. the eeprom can also be used for non- volatile storage of system and/or battery usage statis- tics. a maxim 1-wire (ds2775/ds2776) or 2-wire (ds2777/ds2778) interface provides serial communica-tion to access measurement and capacity data regis- ters, control registers, and user memory. the ds2776/ds2778 use the sha-1 hash algorithm in a challenge-response pack authentication protocol for battery-pack verification. applications low-cost notebooksumpcs dslr cameras video cameras commercial and military radios portable medical equipment features ? high-side nfet drivers and protection circuitry ? precision voltage, temperature, and currentmeasurement system ? cell-capacity estimation from coulomb count,discharge rate, temperature, and cell characteristics ? estimates cell aging between learn cycles ? uses low-cost sense resistor ? allows calibration of gain and temperaturecoefficient ? programmable thresholds for overvoltage andovercurrent ? pack authentication using sha-1 algorithm(ds2776/ds2778) ? 32-byte parameter eeprom ? 16-byte user eeprom ? maxim 1-wire interface with 64-bit unique id(ds2775/ds2776) ? 2-wire interface with 64-bit unique id(ds2777/ds2778) ? 3mm x 5mm, 14-pin tdfn lead-free package ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ________________________________________________________________ maxim integrated products 1 ordering information 19-4688; rev 4; 6/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part pin-package top mark ds2775 g+ 14 tdfn-ep* d2775 ds2775g+t&r 14 tdfn-ep* d2775 ds2776 g+ 14 tdfn-ep* d2776 ds776g+t&r 14 tdfn-ep* d2776 ds2777 g+ 14 tdfn-ep* d2777 ds2777g+t&r 14 tdfn-ep* d2777 ds2778 g+ 14 tdfn-ep* d2778 ds2778g+t&r 14 tdfn-ep* d2778 note: all devices are specified over the -20? to +70? oper- ating temperature range. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. selector guide appears at end of data sheet. 1-wire is a registered trademark of maxim integrated products, inc. downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (v dd = +4.0v to +9.2v, t a = -20? to +70?, unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on pls, cp, cc, dc pins relative to v ss .....................................................-0.3v to +18v voltage range on v dd , v in1 , v in2 , src pins relative to v ss ....................................................-0.3v to +9.2v voltage range on all other pins relative to v ss ..-0.3v to +6.0v continuous sink current, pio, dq......................................20ma continuous sink current, cc, dc.......................................10ma operating temperature range ...........................-20? to +70? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units sleep mode, t a +50c 3 5 i dd0 sleep mode, t a > +50c 10 i dd1 active mode 80 135 supply current i dd2 active mode during sha-1 computation 120 300 a temperature accuracy t err -3 +3 c 2.0v v in1 4.6v, 2.0v (v in2 - v in1 ) 4.6v, 0c t a +50c -35 +35 2.0v v in1 4.6v, 2.0v (v in2 C v in1 ) 4.6v, t a = +25c -22 22 voltage accuracy 2.0v v in1 4.6v, 2.0v (v in2 - v in1 ) 4.6v -50 +50 mv input resistance (v in1 , v in2 ) 15 m current resolution i lsb 1.56 v current full scale i fs -51.2 +51.2 mv current gain error i gerr -1 +1 % fs current offset i oerr 0c t a +70c (note 1) -9.375 9.375 vh accumulated current offset q oerr 0c t a +70c (note 1) -255 0 vh/day 0c t a +50c -2 +2 time-base error t err -3 +3 % cp output voltage (v cp - v src ) v gs i out = 0.9a 4.4 4.7 5 v cp startup time t scp ce = 0, de = 0, c cp = 0.1f, active mode 200 ms output high: cc, dc v ohcp i oh = 100a (note 2) v cp - 0.4 v output low: cc v olcc i ol = 100a v src + 0.1 v output low: dc v oldc i ol = 100a v src + 0.1 v dq, pio voltage range -0.3 +5.5 v dq, pio, sda, scl input logic-high v ih 1.5 v dq, pio, sda, scl input logic-low v il 0.6 v ovd input logic-high v ih v bat - 0.2 v ovd input logic-low v il v ss + 0.2 v downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = +4.0v to +9.2v, t a = -20? to +70?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dq, pio, sda output logic-low v ol i ol = 4ma 0.4 v dq, pio pullup current i pu sleep mode, v pin = (v dd - 0.4v) 30 100 200 na dq, pio, sda, scl pulldown current i pd active mode, v pin = 0.4v 30 100 200 na dq input capacitance c dq 50 pf dq sleep timeout t sleep dq < v il 2 9 s pio, dq wake debounce t wdb sleep mode 100 ms sha-1 computation timing (ds2776/ds2778 only)(v dd = +4.0v to +9.2v, t a = 0? to +70?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units computation time t comp 30 ms electrical characteristics: protection circuit(v dd = +4.0v to +9.2v, t a = 0? to +50?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units v ov = 1110111b 4.438 4.473 4.508 overvoltage detect v ov v ov = 1100011b 4.242 4.277 4.312 v charge-enable voltage v ce relative to v ov -100 mv undervoltage detect v uv programmable in control register 0x60h, uv[1:0] = 10 2.415 2.450 2.485 v oc = 11b -60 -75 -90 overcurrent detect: charge v coc oc = 00b -12.5 -25 -38 mv oc = 11b 80 100 120 overcurrent detect: discharge v doc oc = 00b 25 38 50 mv sc =1b 240 300 360 short-circuit current detect v sc sc = 0b 120 150 180 mv overvoltage delay t ovd (note 3) 600 1400 ms undervoltage delay t uvd (note 3) 600 1400 ms overcurrent delay t ocd 8 10 12 ms short-circuit delay t scd 80 120 160 s charger-detect hysteresis v cd v uv condition 50 mv test threshold v tp coc, doc condition 0.4 1.0 1.2 v doc condition 20 40 80 test current i tst coc condition -45 -60 -95 a pls pulldown current i ppd sleep mode 200 400 630 a recovery current i rc v uv condition, max: v pls = 15v, v dd = 1.4v; min: v pls = 4.2v, v dd = 2v 3.3 8 13 ma downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 4 _______________________________________________________________________________________ eeprom reliability specification(v dd = +4.0v to +9.2v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units eeprom copy time t eec 10 ms eeprom copy endur ance n eec t a = +50c 50,000 cycles electrical characteristics: 1-wire interface, standard (ds2775/ds2776 only)(v dd = +4.0v to +9.2v, t a = -20? to +70?.) parameter symbol conditions min typ max units time slot t slot 60 120 s recovery time t rec 1 s write-zero low time t low0 60 120 s write-one low time t low1 1 15 s read data valid t rdv 15 s reset time high t rsth 480 s reset time low t rstl 480 960 s presence-detect high t pdh 15 60 s presence-detect low t pdl 60 240 s electrical characteristics: 1-wire interface, overdrive (ds2775/ds2776 only)(v dd = +4.0v to +9.2v, t a = -20? to +70?.) parameter symbol conditions min typ max units time slot t slot 6 16 s recovery time t rec 1 s write-zero low time t low0 6 16 s write-one low time t low1 1 2 s read data valid t rdv 2 s reset time high t rsth 48 s reset time low t rstl 48 80 s presence-detect high t pdh 2 6 s presence-detect low t pdl 8 24 s downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication _______________________________________________________________________________________ 5 electrical characteristics: 2-wire interface (ds2777/ds2778 only)(v dd = +4.0v to +9.2v, t a = -20? to +70?.) parameter symbol conditions min typ max units scl clock frequency f scl (note 4) 0 400 khz bus-free time between a stop and start condition t buf 1.3 s hold time (repeated) start condition t hd:sta (note 5) 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (notes 6, 7) 0 0.9 s data setup time t su:dat (note 6) 100 ns rise time of both sda and scl signals t r 20 + 0.1c b 300 ns fall time of both sda and scl signals t f 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 s spike pulse widths suppressed by input filter t sp (note 8) 0 50 ns capacitive load for each bus line c b (note 9) 400 pf scl, sda input capacitance c bin 60 pf note 1: accumulation bias and offset bias registers set to 00h. nben bit set to 0. note 2: measurement made with v src = +8v, v gs driven with external +4.5v supply. note 3: overvoltage (ov) and undervoltage (uv) delays (t ovd , t uvd ) are reduced to zero seconds if the ov or uv condition is detected within 100ms of entering active mode. note 4: timing must be fast enough to prevent the ds2777/ds2778 from entering sleep mode due to bus low for period > t sleep . note 5: f scl must meet the minimum clock low time plus the rise/fall times. note 6: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 7: this device internally provides a hold time of at least 75ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 8: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. note 9: c b is total capacitance of one bus line in pf. downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 6 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) discharge-overcurrent protection delay ds2775/6/7/8 toc01 dc fetgate 2v/div2v/div 0v0v 0v 0v 1v/div 20mv/div dc fetsource v gs v sns 25m sense resistorwith discharge- overcurrent threshold = 38mv time (ms) 18 16 14 12 10 8 6 4 2 02 0 cc fet gate turn-off during charge-overcurrent event ds2775/6/7/8 toc02 cc fetgate 2v/div2v/div 0v0v 0v 0v 1v/div 20mv/div cc fetsource v gs cc fet v sns 25m sense resistorwith charge- overcurrent threshold = 25mv time ( s) 45 40 35 30 25 20 15 10 5 05 0 dc fet gate turn-off during short-circuit event ds2775/6/7/8 toc03 dc fetgate 2v/div 0v0v 0v 0v 2v/div1v/div 50mv/div dc fetsource v gs dc fet v sns 25m sense resistorwith short-circuit threshold = 150mv time ( s) 18 16 14 12 10 8 6 4 2 02 0 short-circuit protection delay ds2775/6/7/8 toc04 dc fetgate 2v/div 0v0v 0v 0v 2v/div1v/div 100mv/div dc fetsource v gs dc fet v sns 25m sense resistorwith short-circuit threshold = 150mv time ( s) 180 160 140 120 100 80 60 40 20 0 200 voltage measurement accuracy ds2775/6/7/8 toc05 v inx (v) accuracy (mv) 4 3 2 1 2 4 6 8 10 12 14 16 18 20 0 0 +70 c -20 c +25 c charge-pump startup exiting sleep mode (v dd = 8v no load on pk+) ds2775/6/7/8 toc06 time (ms) voltage (v) 90 80 10 20 30 50 60 40 70 0 2 3 4 5 6 7 8 -2 0 100 2.75v 12.6v downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication _______________________________________________________________________________________ 7 current measurement accuracy ds2775/6/7/8 toc07 v sns (mv) accuracy ( v) 0.048 0.028 0.008 -0.012 -0.032 -75 -25 25 75 125 -125 -0.052 +70 c -20 c +25 c i rc vs. v dd ds2775/6/7/8 toc08 v dd (v) i rc (ma) 5 4 3 2 1 1 2 3 4 5 6 70 06 1k resistor from pls to pk+ current measurement offset vs. temperature ds2775/6/7/8 toc09 temperature ( c) lsb (1.5625 v) 60 40 20 0 -4 -3 -2 -1 0 1 2 -5 -20 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 8 _______________________________________________________________________________________ pin description pin name function 1 cc charge control. charge fet control output. 2 v dd chip-supply input. bypass with 0.1f to v ss . 3 dc discharge control. discharge fet control output. 4 v in2 battery voltage sense input 2. connect to highest voltage potential positive cell terminal through decoupling network. 5 v in1 battery voltage sense input 1. connect to lowest voltage potential posi tive cell terminal through decoupling network. 6 vb regulated operating voltage. bypass with 0.1f to v ss . 7 v ss device ground. chip ground and battery-side sense resistor input. 8 sns sense resistor connection. pack-side sense resistor sens e input. 9 pio programmable i/o. can be configured as wake input. 10 pls pack plus terminal sense input. used to detect the removal of short-ci rcuit, discharge overcurrent, and charge overcurrent conditions. 11 sda/dq data input/output. serial data i/o, includes weak pulldown to detect system disconnect and can be configured as wake input for 1-wire devices. 12 scl/ovd serial clock input/overdrive select. communication clock for 2-wire dev ices/overdrive select pin for 1-wire devices. 13 src protection mosfet source connection. used as a reference for the charge pump . 14 cp charge pump output. generates gate drive voltage for protection fets. byp ass with 0.47f to src. ep exposed pad. connect to ground or leave unconnected. top view tdfn (3mm 5mm) 1 cc 2 v dd 3 dc 4 v in2 5 v in1 6 vb 7 v ss 14 cp ep 13 src 12 scl/ovd 11 sda/dq 10 pls 9 pio 8 sns + ds2775ds2776 ds2777 ds2778 pin configuration downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 block diagram li+ protector power-mode control voltage current 10-bit + sign adc/mux fuelpack algorithm fet drivers charge pump 15-bit + sign adc temperature precision analog oscillator vref pin drivers and power switch control pio logic communication interface ds2775?s2778 control and status registers 16-byte user eeprom 32-byte parameter eeprom pls voltage regulator v dd vb vb internal ccdc cp v in2 v in1 sns sda/dq scl/ovd pio v ss fuelpack is a trademark of maxim integrated products, inc. 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication _______________________________________________________________________________________ 9 downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 10 ______________________________________________________________________________________ ds2775/ds2776 typical application circuit ds2775ds2776 plsdq vb pio v dd v in2 v in1 cp v ss ovd sns src cc src dc 1k 150 r sns 1k 1k 150 1k 1k 470 pk+ pk- data 0.1 f 0.47 f 0.1 f 5.1v ds2777/ds2778 typical application circuit ds2777ds2778 plssda vb pio scl v dd v in2 v in1 cp v ss sns src cc src dc 1k 150 r sns 1k 1k 150 1k 1k 470 pk+ pk- sda 150 scl 0.1 f 0.47 f 0.1 f 5.1v 5.1v downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 11 detailed description the ds2775?s2778 function as an accurate fuelgauge, li+ protector, and sha-1-based authentication token (sha-1-based authentication available only on the ds2776/ds2778). the fuel gauge provides accu- rate estimates of remaining capacity and reports timely voltage, temperature, and current measurement data. capacity estimates are calculated from a piecewise lin- ear model of the battery performance over load and temperature along with system parameters for charge and end-of-discharge conditions. the algorithm para- meters are user programmable and can be modified within the pack. critical capacity and aging data are periodically saved to eeprom in case of short-circuit or deep-depletion events. the li+ protection function ensures safe, high-perfor- mance operation. nfet protection switches are driven with a charge pump that maintains gate drive as the cell voltage decreases. the high-side topology pre- serves the ground path for serial communication while eliminating the parasitic charge path formed when the fuel-gauge ic is located inside the protection fets in a low-side configuration. the thresholds for overvoltage, undervoltage, overcurrent, and short-circuit current are user programmable for customization to each cell and application. the 32-bit-wide sha-1 engine with 64-bit secret and 64-bit challenge words resists brute force and other attacks with financial-level hmac security. the chal- lenge of managing secrets in the supply chain is addressed with the compute next secret feature. the unique serial number or rom id can be used to assign a unique secret to each battery. power modes the ds2775?s2778 have two power modes: activeand sleep. on initial power-up, the ds2775?s2778 default to active mode. in active mode, the ds2775 ds2778 are fully functional with measurements and capacity estimation registers continuously updated. the protector circuit monitors battery pack, cell volt- ages, and battery current for safe conditions. the pro- tection fet gate drivers are enabled when conditions are deemed safe. also, the sha-1 authentication func- tion is available in active mode. when an sha-1 com- putation is performed, the supply current increases to i dd2 for t sha . in sleep mode, the ds2775?s2778 con- serve power by disabling measurement and capacityestimation functions, but preserve register contents. gate drive to the protection fets is disabled in sleep; the sha-1 authentication feature is not operational. the ic enters sleep mode under two different condi- tions: bus low and undervoltage. an enable bit makes entry into sleep optional for each condition. sleep mode is not entered if a charger is connected (v pls > v dd + v cd ) or if a charge current of 1.6mv/r sns measured from sns to v ss . the ds2775?s2778 exit sleep mode upon charger connection or a low-to-high transition onany communication line. the bus-low condition, where all communication lines are low for t sleep , indicates pack removal or system shutdown in which the buspullup voltage, v pullup , is not present. the power mode (pmod) bit must be set to enter sleep when abus-low condition occurs. after the ds2775?s2778 enter sleep due to a bus-low condition, it is assumed that no charge or discharge current flows and that coulomb counting is unnecessary. the second condition to enter sleep is an undervoltage condition, which reduces battery drain due to the ds2775?s2778 supply current and prevents overdis- charging the cell. the ds2775?s2778 transition to sleep mode if the v in1 or v in2 voltage is less than v uv and the undervoltage enable (uven) bit is set. thecommunication bus must be in a static state, that is, with dq (sda and scl for 2-wire) either high or low for t sleep . the ds2775?s2778 transition from sleep mode to active mode when dq (sda and scl for2-wire) changes logic state. see figures 1 and 2 for more information on sleep-mode state. the ds2775?s2778 have a ?ower switch?capability for waking the device and enabling the protection fets when the host system is powered down. a simple dry contact switch on the pio pin or dq pin can be used to wake up the battery pack. the power-switch function is enabled using the pspio and psdq configuration bits in the control register. when pspio or psdq are set and sleep mode is entered through the pmod condition*, the pio and dq pins pull high, respectively. sleep mode is exited upon the detection of a low-going transition on pio or dq. pio has a 100ms debounce period to filter out glitches that can be caused when a sleeping battery is inserted into a system. * the ?ower switch?feature is disabled if sleep mode is entered because of a uv condition. downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 12 ______________________________________________________________________________________ li+ protection circuitry during active mode, the ds2775?s2778 constantlymonitor sns, v in1 , v in2 , and pls to protect the battery from overvoltage (overcharge), undervoltage (overdis-charge), and excessive charge and discharge currents (overcurrent, short circuit). table 1 summarizes the conditions that activate the protection circuit, the response of the ds2775?s2778, and the thresholds that release the ds2775?s2778 from a protection state. figure 3 shows li+ protection circuitry example waveforms. overvoltage (ov) if either of the voltages on (v in2 - v in1 ) or (v in1 - v ss ) exceeds the overvoltage threshold, v ov , for a period longer than overvoltage delay, t ovd , the cc pin is dri- ven low to shut off the external charge fet. the dc out-put remains high during overvoltage to allow discharging. when (v in2 - v in1 ) and (v in1 - v ss ) falls below the charge-enable threshold, v ce , the ds2775?s2778 turn the charge fet on by driving cchigh. the ds2775?s2778 drive cc high before [(v in2 -v in1 ) and (v in1 - v ss )] < v ce if a discharge condition persists with v sns 1.2mv and [(v in2 - v in1 ) and (v in1 - v ss )] < v ov . active pmod = 0 uven = 0 sleep pspio = 0 psdq = 0 rising edge on dq charger detect pull dq low charger detect active pmod = 0 uven = 1 sleep pspio = 0 psdq = 1 v in1 or v in2 < v uv pull pio low rising edge on dq charger detect active pmod = 1 uven = 0 sleep pspio = 1 psdq = 0 pull dq low for t sleep pull dq low for t sleep pull dq low pull pio low charger detect active pmod = 1 uven = 1 sleep pspio = 1 psdq = 1 v in1 or v in2 < v uv figure 1. sleep-mode state diagram for ds2775/ds2776 active pmod = 0 uven = 0 sleep pspio = 0 psdq = x rising edge on sda or scl charger detect v in1 or v in2 < v uv charger detect active pmod = 0 uven = 1 sleep pspio = 0 psdq = x rising edge on sda or scl pull pio low charger detect pull sda and scl low for t sleep active pmod = 1 uven = 0 sleep pspio = 1 psdq = x rising edge on sda or scl pull sda and scl low for t sleep pull pio low charger detect v in1 or v in2 < v uv active pmod = 1 uven = 1 sleep pspio = 1 psdq = x rising edge on sda or scl figure 2. sleep-mode state diagram for ds2777/ds2778 downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 13 activation condition threshold delay response release threshold overvoltage (ov) (note 1) v cell > v ov t ovd cc off both v cell < v ce or (v sns 1.2mv and both v cell < v ov ) (note 1) undervoltage (uv) (note 1) v cell < v uv t uvd cc off, dc off, sleep mode (note 2) v pls > v in2 (charger connected) or (both v cell > v uv and uven = 0) (note 3) overcurrent, charge (coc) v sns < v coc t ocd cc off, dc off v pls < v dd C v tp (charger removed) (note 4) overcurrent, discharge (doc) v sns > v doc t ocd dc off v pls > v dd C v tp (load removed) (note 5) short circuit (sc) v sns > v sc t scd dc off v pls > v dd C v tp (note 5) table 1. li+ protection conditions and ds2775/ds2776 responses note 1: v cell is defined as (v in1 - v ss ) or (v in2 - v in1 ). note 2: sleep mode is only entered if uven = 1. note 3: if v cell < v uv when a charger connection is detected, release is delayed until v cell v uv . the recovery charge path pro- vides an internal current limit (i rc ) to safely charge the battery. note 4: with test current i ppd flowing from pls to v ss (pulldown on pls) enabled. note 5: with test current i tst flowing from v dd to pls (pullup on pls). v ov v ce v uv v in v sns -v coc 0 v doc v sc t ovd t ovd t ocd t uvd t uvd t ocd t sco discharge charge power mode activesleep* *if uven = 1. ccdc v ohcc v cp v dd v cp v pls figure 3. li+ protection circuitry example waveforms downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 14 ______________________________________________________________________________________ undervoltage (uv) if the average of the voltages on (v in2 - v in1 ) or (v in1 - v ss ) drops below the undervoltage threshold, v uv , for a period longer than undervoltage delay, t uvd , the ds2775?s2778 shut off the charge and dischargefets. if uven is set, the ds2775?s2778 also enter sleep mode. when a charger is detected and v pls > v in2 , the ds2775?s2778 provide a current-limited recovery charge path (i rc ) from pls to v dd to gently charge severely depleted cells. the recovery chargepath is enabled when 0 [(v in2 - v in1 ) and (v in1 - v ss )] < v ce . the fets remain off until (v in2 - v in1 ) and (v in1 - v ss ) exceed v uv . overcurrent, charge direction (coc) charge current develops a negative voltage on v sns with respect to v ss . if v sns is less than the charge overcurrent threshold, v coc , for a period longer than overcurrent delay, t ocd , the ds2775?s2778 shut off both external fets. the charge current path is not re-established until the voltage on the pls pin drops below (v dd - v tp ). the ds2775?s2778 provide a test current of value i ppd from pls to v ss , pulling pls down, in order to detect the removal of the offendingcharge current source. overcurrent, discharge direction (doc) discharge current develops a positive voltage on v sns with respect to v ss . if v sns exceeds the discharge overcurrent threshold, v doc , for a period longer than t ocd , the ds2775?s2778 shut off the external dis- charge fet. the discharge current path is not reestab-lished until the voltage on pls rises above (v dd - v tp ). the ds2775?s2778 provide a test current of valuei tst from v dd to pls, pulling pls up, in order to detect the removal of the offending low-impedance load. short circuit (sc) if v sns exceeds short-circuit threshold, v sc , for a period longer than short-circuit delay, t scd , the ds2775?s2778 shut off the external discharge fet.the discharge current path is not reestablished until the voltage on pls rises above (v dd - v tp ). the ds2775?s2778 provide a test current of value i tst from v dd to pls, pulling pls up, in order to detect the removal of the short circuit.all the protection conditions described are logic anded to affect the cc and dc outputs. cc = ( overvoltage ) and ( undervoltage ) and ( overcurrent , charge direction) and (protection register bit ce = 0) dc = ( undervoltage ) and ( overcurrent , either direction) and ( short circuit ) and (protection register bit de = 0) voltage measurements cell voltages are measured every 440ms. the lowestpotential cell, v in1 , is measured with respect to v ss . the highest potential cell, v in2 , is measured with respect to v in1 . battery voltages are measured with a range of -5v to +4.9951v and a resolution of 4.8828mvand placed in the result register in two? complement form. voltages above the maximum register value are reported as 7fe0h. msb - address 0ch, v in1 - v ss lsb - address 0dh, v in1 - v ss msb - address 1ch, v in2 - v in1 lsb - address 1dh, v in2 - v in1 s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb msb lsb s: sign bit(s), x: reserved units: 4.883mv figure 4. voltage register format downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 15 temperature measurement the ds2775?s2778 use an integrated temperaturesensor to measure battery temperature with a resolution of 0.125?. temperature measurements are updated every 440ms and placed in the temperature register in two? complement form. current measurement in active mode, the ds2775?s2778 continuously mea-sure the current flow into and out of the battery by mea- suring the voltage drop across a low-value current-sense resistor, r sns . the voltage-sense range between sns and v ss is ?1.2mv with a least significant bit (lsb) of 1.5625?. the input linearly converts peak signal ampli-tudes up to 102.4mv as long as the continuous signal level (average over the conversion cycle period) does not exceed ?1.2mv. the adc samples the input differ- entially at 18.6khz and updates the current register at the completion of each conversion cycle (3.52s). charge currents above the maximum register value are reported as 7fffh. discharge currents below the minimum regis- ter value are reported as 8000h. the average current register reports an average cur- rent level over the preceding 28.16s. the register value is updated every 28.16s in two? complement form and represents an average of the eight preceding current register values. msbaddress 0ah lsbaddress 0bh s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb msb lsb s: sign bit(s), x: reserved units: 0.125c figure 5. temperature register format msbaddress 0eh lsbaddress 0fh s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb s: sign bit(s) units: 1.5625v/r sns figure 6. current register format msbaddress 08h lsbaddress 09h s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb s: sign bit(s) units: 1.5625v/r sns figure 7. average current register format downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 16 ______________________________________________________________________________________ current offset correction every 1024th conversion, the adc measures its inputoffset to facilitate offset correction. offset correction occurs approximately once per hour. the resulting cor- rection factor is applied to the subsequent 1023 mea- surements. during the offset correction conversion, the adc does not measure the sense resistor signal. a maximum error of 1/1024 in the accumulated current register (acr) is possible; however, to reduce the error, the current measurement made just prior to the offset conversion is retained in the current register and is substituted for the dropped current measurement in the current accumulation process. therefore the accumu- lated current error due to offset correction is typically much less than 1/1024. current offset bias the current offset bias value (cob) allows a program-mable offset value to be added to raw current measure- ments. the result of the raw current measurement plus cob is displayed as the current measurement result in the current register and is used for current accumula- tion. cob can be used to correct for a static offset error or can be used to intentionally skew the current results and therefore the current accumulation. read and write access is allowed to cob. whenever the cob is writ- ten, the new value is applied to all subsequent current measurements. cob can be programmed in 1.56? steps to any value between -199.7? and +198.1?. the cobr value is stored as a two? complement value in volatile memory and must be initialized through the interface on power-up. the factory default value is 00h. current blanking the current blanking feature modifies current measure-ment result prior to being accumulated in the acr. current blanking occurs conditionally when a current measurement (raw current and cobr) falls in one of two defined ranges. the first range prevents charge currents less than 100? from being accumulated. the second range prevents discharge currents less than 25? in magnitude from being accumulated. charge current blanking is always performed; however, dis- charge current blanking must be enabled by setting the nben bit in the control register. see the control register format description for additional information. current measurement gain the ds2775?s2778? current measurement gain canbe adjusted through the rsgain register, which is facto- ry calibrated to meet the data sheet specified accuracy. rsgain is user accessible and can be reprogrammed after module or pack manufacture to improve the current measurement accuracy. adjusting rsgain can correct for variation in an external sense resistor? nominal value and allows the use of low-cost, nonprecision current- sense resistors. rsgain is an 11-bit value stored in 2 bytes of the parameter eeprom memory block. the rsgain value adjusts the gain from 0 to 1.999 in steps of 0.001 (precisely 2?0). the user must use caution when programming rsgain to ensure accurate current measurement. when shipped from the factory, the gain calibration value is stored in two separate locations in the parameter eeprom block, rsgain, which is reprogram- mable and frsgain, which is read-only. rsgain deter- mines the gain used in the current measurement. the address 7bh s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb s: sign bit(s) units: 1.56v/r sns figure 8. current offset bias register format msbaddress 78h lsbaddress 79h x sc0 oc1 oc0 x 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 msb lsb msb lsb x: reserved units: 2C10 figure 9. rsgain register downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 17 frsgain value is provided to preserve the factory cali-bration value only and is not used to calibrate the current measurement. the 16-bit frsgain value is readable from addresses b0h and b1h. sense-resistor temperature compensation the ds2775?s2778 can temperature compensate thecurrent-sense resistor to correct for variation in a sense resistor? value over temperature. the ds2775?s2778 are factory programmed with the sense-resistor temper- ature coefficient, rstc, set to zero, which turns off the temperature compensation function. rstc is user accessible and can be reprogrammed after module or pack manufacture to improve the current accuracy when using a high-temperature coefficient current- sense resistor. rstc is an 8-bit value stored in the parameter eeprom memory block. the rstc value sets the temperature coefficient from 0 to +7782ppm/? in steps of 30.5ppm/?. the user must program rstc cautiously to ensure accurate current measurement. temperature compensation adjustments are made when the temperature register crosses 0.5? boundaries. the temperature compensation is most effective with the resistor placed as close as possible to the v ss terminal to optimize thermal coupling of the resistor to the on-chiptemperature sensor. if the current shunt is constructed with a copper pcb trace, run the trace under the ds2775?s2778 package whenever possible. current accumulation current measurements are internally summed, or accu-mulated, at the completion of each conversion period with the results displayed in the accumulated currentregister (acr). the accuracy of the acr is dependent on both the current measurement and the conversion time base. the acr has a range of 0 to +409.6mvh with an lsb of 6.25?h. additional registers hold frac- tional results of each accumulation to avoid truncation errors. the fractional result bits are not user accessible. accumulation of charge current above the maximum register value is reported at the maximum value; con- versely, accumulation of discharge current below the minimum register value is reported at the minimum value. charge currents (positive current register values) less than 100? are not accumulated in order to mask the effect of accumulating small positive offset errors over long periods. this effect limits the minimum charge cur- rent, for coulomb counting purposes, to 5ma for r sns = 0.020 and 20ma for r sns = 0.005 (see table 2 for more details).read and write access is allowed to the acr. the acr must be written most significant byte (msb) first, then lsb. whenever the acr is written, the fractional accumulation result bits are cleared. the write must be completed in 3.5s. a write to the acr forces the adc to perform an offset correction conversion and update the internal offset correction factor. the cur- rent measurement and accumulation begin with the second conversion following a write to the acr. to preserve the acr value in case of power loss, the acr value is backed up to eeprom. the acr value is recovered from eeprom on power-up. see the memory map for specific address location and back- up frequency. r sns type of resolution/range v ss - v sns 20m 15m 10m 5m current resolution 1.5625v 78.13a 104.2a 156.3a 312.5a current range 51.2mv 2.56a 3.41a 5.12a 10.2a acr resolution 6.25vh 312.5ah 416.7ah 625ah 1.250mah acr range 409.6mvh 20.48ah 27.30ah 40.96ah 81.92ah table 2. resolution and range vs. sense resistor msbaddress 10h lsbaddress 11h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb units: 6.25v/r sns figure 10. accumulated current register format downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 18 ______________________________________________________________________________________ accumulation bias in some designs a systematic error or an applicationpreference requires the application of an arbitrary bias to the current accumulation process. the current accumulation bias register (cab) allows a user-pro- grammed constant positive or negative polarity bias to be included in the current accumulation process. the value in cab can be used to estimate battery currents that do not flow through the sense resistor, estimate battery self-discharge, or estimate current levels below the current measurement resolution. the user-pro- grammed two? complement value, with bit weighting the same as the current register, is added to the acr once per current conversion cycle. cab is loaded on power-up from eeprom memory. cycle counter the cycle counter is an absolute count of the cumula-tive discharge cycles. this register is intended to act as a ?ell odometer.?the lsb is two cycles, which allows a maximum count of 510 discharge cycles. the register does not loop. once the maximum value is reached, the register is clamped. this register is read and write accessible while the parameter eeprom memory block (block 1) is unlocked. the cycle count register becomes read-only once the eeprom block is locked. capacity estimation algorithm remaining capacity estimation uses real-time mea-sured values and stored parameters describing the cell characteristics and application operating limits. figure 13 describes the algorithm inputs and outputs. modeling cell characteristics to achieve reasonable accuracy in estimating remain-ing capacity, the cell performance characteristics over temperature, load current, and charge-termination point must be considered. since the behavior of li+ cells is nonlinear, these characteristics must be included in the capacity estimation to achieve an acceptable level of accuracy in the capacity estimation. the fuelpack method used in the ds2775?s2778 is described in general in application note 131: lithium-ion cell fuel gauging with maxim battery monitor ics. to facilitate efficient implementation in hardware, a modified versionof the method outlined in application note 131 is used to store cell characteristics in the ds2775?s2778. full and empty points are retrieved in a lookup process that retraces a piecewise linear model consisting of three model curves named full, active empty, and standby empty. each model curve is constructed with five line segments, numbered 1 through 5. above +40?, the segment 5 model curves extend infinitely with zero slope, approximating the nearly flat change in capacity of li+ cells at temperatures above +40?. segment 4 of each model curves originates at +40? on its upper end and extends downward in temperature to the junction with segment 3. segment 3 joins with segment 2, which in turn joins with segment 1. segment 1 of each model curve extends from the junction with segment 2 to infi- nitely colder temperatures. the three junctions or break- points that join the segments (labeled tbp12, tbp23, and tbp34 in figure 14) are programmable in 1? increments from -128? to +40?. the slope or deriva- tive for segments 1, 2, 3, and 4 are also programmable over a range of 0 to 15,555ppm in steps of 61ppm. address 61h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb s: sign bit(s) units: 6.25v/r sns figure 11. current accumulation bias register format address 1eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb units: 2 cycles figure 12. cycle counter register format downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 19 capacity lookup available capacity calculation acr housekeeping age estimator learn function voltage (r) full full(t) (r) active empty ae(t) (r) standby empty se(t) (r) remaining active-absolute capacity (raac) mah (r) remaining standby-absolute capacity (rsac) mah (r) remaining active-relative capacity (rarc) % (r) remaining standby-relative capacity (rsrc) % (r) temperature (r) current (r) average current (r) accumulatedcurrent (acr) (rw) age scalar (as)(1 byte ee) aging capacity (ac)(2 bytes ee) sense-resistor prime (rsnsp)(1 byte ee) charge voltage (vchg)(1 byte ee) minimum charge current (imin)(1 byte ee) active-empty voltage (vae)(1 byte ee) active-empty current (iae)(1 byte ee) cell model parameters (eeprom) user memory (eeprom) 16 bytes cycle counter (eeprom) figure 13. top-level algorithm diagram full the full curve defines how the full point of a given celldepends on temperature for a given charge termina- tion. the application? charge termination method should be used to determine the table values. the ds2775?s2778 reconstruct the full line from cell char- acteristic table values to determine the full capacity of the battery at each temperature. reconstruction occurs in one-degree temperature increments. active empty the active-empty curve defines the variation of theactive-empty point over temperature. the active-empty point is defined as the minimum voltage required for system operation at a discharge rate based on a high- level load current (one that is sustained during a high- power operating mode). this load current is programmed as the active-empty current (iae), and should be a 3.5s average value to correspond to values downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 20 ______________________________________________________________________________________ 100% segment 1 derivative (ppm/ c) full active empty standby empty segment 2 segment 3 segment 4 +40 c tbp34 tbp23 tbp12 segment 5 cell characterization cell characterization data figure 14. cell model example diagram read from the current register. the specified minimumvoltage, or active-empty voltage (vae), should be a 110ms average value to correspond to the values read from the voltage register. the vae value represents the average of the two cell? voltages, v in1 and v in2 . the ds2775?s2778 reconstruct the active-empty line fromthe cell characteristic table to determine the active- empty capacity of the battery at each temperature. reconstruction occurs in one-degree temperature increments. standby empty the standby-empty curve defines the variation of thestandby-empty point over temperature. the standby- empty point is defined as the minimum voltage required for standby operation at a discharge rate dictated by the application standby current. in typical handheld applications, standby empty represents the point that the battery can no longer support dram refresh and thus the standby voltage is set by the minimum dramvoltage-supply requirements. in other applications, standby empty can represent the point that the battery can no longer support a subset of the full application operation, such as games or organizer functions. the standby-load current and voltage are used for deter- mining the cell characteristics but are not programmed into the ds2775?s2778. the ds2775?s2778 recon- struct the standby-empty line from the cell characteris- tic table to determine the standby-empty capacity of the battery at each temperature. reconstruction occurs in one-degree temperature increments. cell model construction the model is constructed with all points normalized tothe fully charged state at +40?. all values are stored in the cell parameter eeprom block. the +40? full value is stored in ?h with an lsb of 6.25?h. the +40? active-empty value is stored as a percentage of +40? downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 21 full with a resolution of 2 -10 . standby empty at +40? is, by definition, zero and therefore no storage is required.the slopes (derivatives) of the four segments for each model curve are stored in the cell parameter eeprom block as ppm/?. the breakpoint temperatures of each segment are stored there also (refer to application note 3584: storing battery fuel gauge parameters in ds2780 for more details on how values are stored). an example of data stored in this manner is shown in table 3. application parameters in addition to cell model characteristics, several appli-cation parameters are needed to detect the full and empty points, as well as calculate results in mah units. sense resistor prime (rsnsp) rsnsp stores the value of the sense resistor for use incomputing the absolute capacity results. the value is stored as a 1-byte conductance value with units of mhos (1/ ). rsnsp supports resistor values of 1 to 3.922m . rsnsp is located in the parameter eeprom block. rsnsp = 1/r sns (units of mhos; 1/ ) charge voltage (vchg) vchg stores the charge voltage threshold used todetect a fully charged state. the voltage is stored as a 1-byte value with units of 19.5mv and can range from 0 to 4.978v. vchg should be set marginally less than the average cell voltage at the end of the charge cycle to ensure reliable charge termination detection. vchg is located in the parameter eeprom block. temperature cell model parameters (eeprom) lookup function full(t) ae(t) se(t) figure 15. lookup function diagram manufacturers rated cell capacity: 1000mah charge voltage: 4.2v termination current: 50ma active empty (v): 3.0v standby empty (i): 300ma sense resistor: 0.020 segment breakpoints tbp12 = -12c tbp23 = 0c tbp34 = 18c calculated value +40c nominal (mah) segment 1 (ppm/c) segment 2 (ppm/c) segment 3 (ppm/c) segment 4 (ppm/c) full 1051 3601 3113 1163 854 active empty 2380 1099 671 305 standby empty 1404 427 244 183 table 3. example cell characterization table (normalized to +40?) downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 22 ______________________________________________________________________________________ minimum charge current (imin) imin stores the charge-current threshold used to detecta fully charged state. it is stored as a 1-byte value with units of 50? (imin x r sns ) and can range from 0 to 12.75mv. assuming r sns = 20m , imin can be pro- grammed from 0 to 637.5ma in 2.5ma steps. iminshould be set marginally greater than the charge cur- rent at the end of the charge cycle to ensure reliable charge termination detection. imin is located in the parameter eeprom block. active-empty voltage (vae) vae stores the voltage threshold used to detect theactive-empty point. the value is stored in 1 byte with units of 19.5mv and can range from 0 to 4.978v. vae is stored as an average of the cell? voltages. vae is locat- ed in the parameter eeprom block. see the modeling cell characteristics section for more information. active-empty current (iae) iae stores the discharge-current threshold used todetect the active-empty point. the unsigned value rep- resents the magnitude of the discharge current and is stored in 1 byte with units of 200? and can range from 0 to 51.2mv. assuming r sns = 20m , iae can be pro- grammed from 0 to 2550ma in 10ma steps. iae is locat-ed in the parameter eeprom block. see the modeling cell characteristics section for more information. aging capacity (ac) ac stores the rated cell capacity, which is used to esti-mate the decrease in battery capacity that occurs dur- ing normal use. the value is stored in 2 bytes in the same units as the acr (6.25?h). when set to the man- ufacturer? rated cell capacity, the aging estimation rate is approximately 2.4% per 100 cycles of equivalent full capacity discharges. partial discharge cycles are added to form equivalent full capacity discharges. the default aging estimation results in 88% capacity after 500 equivalent cycles. the aging estimation rate can be adjusted by setting the ac to a value other than the cell manufacturer? rating. setting ac to a lower value accelerates the aging estimation rate. setting ac to a higher value retards the aging estimation rate. the ac is located in the parameter eeprom block. age scalar (as) as adjusts the cell capacity estimation results down-ward to compensate for aging. the as is a 1-byte value that has a range of 49.2% to 100%. the lsb is weight- ed at 0.78% (precisely 2 -7 ). a value of 100% (128 deci- mal or 80h) represents an unaged battery. a value of95% is recommended as the starting as value at the time of pack manufacture to allow the learning of a larg-er capacity on batteries that have an initial capacity greater than the rated cell capacity programmed in the cell characteristic table. the as is modified by aging estimation introduced under aging capacity and by the learn function. batteries are typically considered worn out when the full capacity reaches 80% of the rated capacity; therefore, the as value is not required to range to 0%. it is clamped to 50% (64 decimal or 40h). if a value of 50% is read from the as, the host should prompt the user to initiate a learning cycle. the host system has read and write access to the as; however, caution should be exercised when writing it to ensure that the cumulative aging estimate is not over- written with an incorrect value. the as is automatically saved to eeprom. the eeprom value is recalled on power-up. capacity estimation operation cycle-count-based aging estimation as previously discussed, the as register value isadjusted occasionally based on cumulative discharge. as the acr register decrements during each discharge cycle, an internal counter is incremented until equal to 32 times the ac. the as is then decremented by one, resulting in a decrease of the scaled full battery capaci- ty by 0.78% (approximately 2.4% per 100 cycles). the internal counter is reset in the event of a learn cycle. see the aging capacity (ac) section for recommenda- tions on customizing the age estimation rate. learn function because li+ cells exhibit charge efficiencies near unity,the charge delivered to a li+ cell from a known empty point to a known full point is a dependable measure of the cell? capacity. a continuous charge from empty to full results in a learn cycle. first, the active-empty point must be detected. the learn flag (learnf) is set at this point. then, once charging starts, the charge must con- tinue uninterrupted until the battery is charged to full. upon detecting full, the learnf is cleared, the charge- to-full (chgtf) flag is set, and the as is adjusted according to the learned capacity of the cell. full capacity estimation based on the learn function is more accurate than the cycle-count-based estimation introduced under aging capacity. the learn function reflects the current performance of the cell. cycle- count-based estimation is an approximation derived from the manufacturer? recommendation for a typical cell. therefore, the internal counter used for cycle- downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 23 count-based estimation is reset after a learn cycle. thecycle-count-based estimation is used only in the absence of a learn cycle. acr housekeeping the acr value is adjusted occasionally to maintain thecoulomb count within the model curve boundaries. when the battery is charged to full (chgtf set), the acr is set equal to the age-scaled full lookup value at the present temperature. if a learn cycle is in progress, correction of the acr value occurs after the as is updated. when an empty condition is detected (learnf and/or aef set), the acr adjustment is conditional: if the aef is set and the learnf is not set, the active-empty point was not detected. the battery islikely below the active-empty capacity of the model. the acr is set to the active-empty model value at present temperature only if it is greater than the active-empty model value at present temperature. if the aef is set, the learnf is not set, and the acr is below the active-empty model value at presenttemperature, the acr is not updated. if the learnf is set, the battery is at the active- empty point and the acr is set to the active-emptymodel value. full detect full detection occurs when the average of v in1 and v in2 voltage registers remain continuously above the charge voltage (vchg) threshold for the duration of twoaverage current (iavg) readings, and both iavg read- ings are below terminating current (imin). the two con- secutive iavg readings must also be positive and nonzero (>16 lsb). this ensures that removing the bat- tery from the charger does not result in a false detec- tion of full. full detect sets the charge to full (chgtf) bit in the status register. active-empty point detect active-empty point detection occurs when the averageof v in1 and v in2 voltage registers drops below the vae threshold and the two previous current readings areabove iae. this captures the event of the battery reach- ing the active-empty point. note that the two previous current readings must be negative and greater in mag- nitude than iae (i.e., a larger discharge current than specified by the iae threshold). qualifying the voltage level with the discharge rate ensures that the active-empty point is not detected at loads much lighter than those used to construct the model. also, the active- empty point must not be detected when a deep dis- charge at a very light load is followed by a load greater than iae. either case would cause a learn cycle on the following charge to include part of the standby capacity in the measurement of the active capacity. active- empty point detection sets the learn flag (learnf) bit in the status register. note: do not confuse the active-empty point with the active-empty flag. the active-empty flag is set onlywhen the vae threshold is passed. result registers the ds2775?s2778 process measurement and cellcharacteristics on a 3.5s interval and yield seven result registers. the result registers are sufficient for direct display to the user in most applications. the host sys- tem can produce customized values for system use or user display by combining measurement, result, and user eeprom values. full(t) the full capacity of the battery at the present tempera-ture is reported normalized to the +40? full value. this 15-bit value reflects the cell model full value at the given temperature. the full(t) register reports values between 100% and 50% with a resolution of 61ppm (precisely 2 -14 ). though the register format permits val- ues greater than 100%, the register value is clamped toa maximum value of 100%. active empty, ae(t) the active-empty capacity of the battery at the presenttemperature is reported normalized to the +40? full value. this 13-bit value reflects the cell model active- empty value at the given temperature. the ae(t) regis- ter reports values between 0% and 49.8% with a resolution of 61ppm (precisely 2 -14 ). standby empty, se(t) the standby-empty capacity of the battery at the pre-sent temperature is reported normalized to the +40? full value. this 13-bit value reflects the cell model standby-empty value at the current temperature. the se(t) register reports values between 0% and 49.8% with a resolution of 61ppm (precisely 2 -14 ). downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 24 ______________________________________________________________________________________ the raac register reports the capacity available under the current temperature conditions to the the active-emptypoint in absolute units of milliamps/hour (mah). raac is 16 bits. the rsac register reports the remaining battery capacity available under the current temperature conditions to the standby-empty point capacity in absolute units of milliamps/hour (mah). rsac is 16 bits. the rarc register reports the remaining battery capacity available under the current temperature conditions to the active-empty point in relative units of percent (%). rarc is 8 bits. the rsrc register reports the remaining battery capacity available under the current temperature conditions to the standby-empty point capacity in relative units of percent (%). rsrc is 8 bits. calculation of results raac [mah] = (acr[mvh] - ae(t) x full40[mvh]) x rsnsp [mhos]* rsac [mah] = (acr[mvh] - se(t) x full40[mvh]) x rsnsp [mhos]* rarc [%] = 100% x (acr[mvh] - ae(t) x full40[mvh])/{(as x full(t) - ae(t)) x full40[mvh]} rsrc [%] = 100% x (acr[mvh] - se(t) x full40[mvh])/{(as x full(t) - se(t)) x full40[mvh]} * rsnsp = 1/r sns msbaddress 02h lsbaddress 03h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb units: 1.6mah figure 16. remaining active absolute capacity (raac) [mah] msbaddress 04h lsbaddress 05h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb units: 1.6mah figure 17. remaining standby absolute capacity (rsac) [mah] msbCaddress 06h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 msb lsb units: 1% figure 18. remaining active relative capacity (rarc) [%] msbCaddress 07h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 msb lsb units: 1% figure 19. remaining standby relative capacity (rsrc) [%] downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 25 protection, status, and control registers protection register format the protection register reports events detected by the li+ safety circuit on bits [3:2]. bits 0 and 1 are used to disablethe charge and discharge fet gate drivers. bits [3:2] are set by internal hardware only. bits 2 and 3 are cleared by hardware only. bits 0 and 1 are set on power-up and a transition from sleep to active modes. while in active mode, these bits can be cleared to disable the fet gate drive of either or both fets. setting these bits only turns on the fets if there are no protection faults. protection register (00h) bits 7 to 4: reserved.bit 3: charge control flag (cc). cc indicates the logic state of the cc pin driver. the cc flag is set to indicate cc high and is cleared to indicate cc low. the cc flag is read-only.bit 2: discharge control flag (dc). dc indicates the logic state of the dc pin driver. dc flag is set to indicate dc high and is cleared to indicate dc low. dc flag is read-only.bit 1: charge-enable bit (ce). ce must be set to allow the cc pin to drive the charge fet to the on state. ce acts as an enable input to the safety circuit. if all safety conditions are met and ce is set, the cc pin drives to v cp . if ce is cleared, the cc pin is driven low to disable the charge fet. the power-up default state of ce is 1.bit 0: discharge-enable bit (de). de must be set to allow the dc pin to drive the discharge fet to the on state. de acts as an enable input to the safety circuit. if all safety conditions are met and de is set, the dc pin drives to v cp . if de is cleared, the dc pin is driven low to disable the discharge fet. the power-up default state of de is 1. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x cc dc ce de downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 26 ______________________________________________________________________________________ status register format the status register contains bits that report the device status. all bits are set internally. the chgtf, aef, sef, andlearnf bits are read-only. status register (01h) bit 7: charge-termination flag (chgtf). chgtf is set to indicate that the average of the voltages on v in1 and v in2 and the average current register values have persisted above the vchg and below the imin thresholds suffi- ciently long enough to detect a fully charged condition. chgtf is cleared when rarc is less than 90%. chgtf isread-only. bit 6: active-empty flag (aef). aef is set to indicate that the battery is at or below the active-empty point. aef is set when the average of the voltages on v in1 and v in2 is less than the vae threshold. aef is cleared when rarc is greater than 5%. aef is read-only.bit 5: standby-empty flag (sef). sef is set to indicate rsrc is less than 10%. sef is cleared when rsrc is greater than 15%. sef is read-only.bit 4: learn flag (learnf). learnf indicates that the current-charge cycle can be used to learn the battery capacity. learnf is set when the active-empty point is detected. this occurs when the average of the voltages onv in1 and v in2 drops below the vae threshold and the two previous current register values were negative and greater in magnitude than the iae threshold. see the active-empty point detect section for additional information. learnf is cleared when any of the following occur: 1) learn cycle completes (chgtf set). 2) current register value becomes negative indicating discharge current flow. 3) acr = 0. 4) acr value is written or recalled from eeprom. 5) sleep mode is entered. learnf is read-only. bit 3 to 0: reserved. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chgtf aef sef learnf x x x x downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 27 control register format all control register bits are read and write accessible. the control register is recalled from parameter eeprommemory at power-up. register bit values can be modified in shadow ram after power-up. power-up default values are saved by using the copy data command. control register (60h) bit 7: negative blanking enable (nben). a value of 1 enables blanking of negative current values up to 25?. a value of 0 disables blanking of negative currents. the power-up default of nben = 0.bit 6: undervoltage enable (uven). a value of 1 allows the ds2775?s2778 to enter sleep mode when the aver- age of the voltages on v in1 and v in2 is less than v uv and dq is stable at either logic level for t sleep . a value of 0 disables transitions to sleep mode during an undervoltage condition.bit 5: power-mode enable (pmod). a value of 1 allows the ds2775?s2778 to enter sleep mode when dq is low for t sleep . a value of 0 disables dq-related transitions to sleep mode. bit 4: read net address op code (rnaop). a value of 0 selects 33h as the op code value for the read net address command. a value of 1 selects 39h as the op code value for the read net address command.bit 3 and 2: undervoltage threshold (vuv[1:0]). sets the voltage at which the part detects an undervoltage condi- tion according to table 4.bit 1: power-switch pio enable (pspio). a value of 1 enables the pio pin as a power-switch input. a value of 0 disables the power-switch input function on pio pin. this control is independent of the psdq state.bit 0: power-switch dq enable (psdq). a value of 1 enables the dq pin as a power-switch input. a value of 0 dis- ables the power-switch input function on dq pin. this control is independent of the pspio state. this bit has noeffect in the ds2777/ds2778. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nben uven pmod rnaop vuv1 vuv0 pspio psdq vuv[1:0] bit field v uv (v) 0 0 2.00 0 1 2.30 1 0 2.45 1 1 2.60 table 4. undervoltage threshold downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 28 ______________________________________________________________________________________ overvoltage threshold register format the 8-bit overvoltage threshold register (vov) sets the overvoltage threshold for the protection circuitry. an over-voltage condition is detected if either of the voltages on v in1 or v in2 exceeds the ov threshold for t ovd . the lsb of the vov register is 2 x 5v/1024 = 31.25mv. the v ov set point can be calculated by the following formula. v ov = (678 + 2 x overvoltage_threshold_register_value) x 5v/1024 example: overvoltage threshold register = 1110110b = 118d v ov = (678 + 2 x 118) x 5v/1024 = 4.46289v overvoltage threshold register (7fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x vov6 vov5 vov4 vov3 vov2 vov1 vov0 vov[6:0] bit field v ov (v) 0 0 0 0 0 0 0 3.311 0 0 0 0 0 0 1 3.320 0 0 0 0 0 1 0 3.330 0 0 0 0 0 1 1 3.340 0 0 0 0 1 0 0 3.350 0 0 0 0 1 0 1 3.359 0 0 0 0 1 1 0 3.369 0 0 0 0 1 1 1 3.379 0 0 0 1 0 0 0 3.389 0 0 0 1 0 0 1 3.398 0 0 0 1 0 1 0 3.408 0 0 0 1 0 1 1 3.418 0 0 0 1 1 0 0 3.428 0 0 0 1 1 0 1 3.438 0 0 0 1 1 1 0 3.447 0 0 0 1 1 1 1 3.457 ... ... vov[6:0] bit field v ov (v) 1 1 1 0 0 0 0 4.404 1 1 1 0 0 0 1 4.414 1 1 1 0 0 1 0 4.424 1 1 1 0 0 1 1 4.434 1 1 1 0 1 0 0 4.443 1 1 1 0 1 0 1 4.453 1 1 1 0 1 1 0 4.463 1 1 1 0 1 1 1 4.473 1 1 1 1 0 0 0 4.482 1 1 1 1 0 0 1 4.492 1 1 1 1 0 1 0 4.502 1 1 1 1 0 1 1 4.512 1 1 1 1 1 0 0 4.521 1 1 1 1 1 0 1 4.531 1 1 1 1 1 1 0 4.541 1 1 1 1 1 1 1 4.551 table 5. vov register programmability downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 29 overcurrent thresholds the overcurrent thresholds are set in the upper nibble of the rsgain register. the oc1 and oc0 bits set the over-current thresholds for the charge and discharge thresholds. the short-circuit threshold is set by the sc0 bit (see tables 6 and 7, respectively, for overcurrent and short-circuit threshold values). the ds2775?s2778 have a built-in fixed delay of t ocd for overcurrent events and t scd for short-circuit events. this means that the current adc must read a value greater than the overcurrent threshold for longer than t ocd and greater than the short-circuit threshold for longer than t scd before turning off the fet. overcurrent and short-circuit events less than their respective delays are ignored. special feature register format all register bits are read and write accessible with default values specified in each bit definition. special feature register (15h) bits 7 to 2: reserved.bit 1: sha idle bit (sha_idle). for the ds2777/ds2778, this bit reads logic 1 while an sha calculation is in progress and reads logic 0 when the calculation is complete.bit 0: pio pin sense and control bit (piob). writing a 0 to the piob bit activates the pio pin open-drain output driver, forcing the pio pin low. writing a 1 to piob disables the output driver, allowing the pio pin to be pulled highor used as an input. reading piob returns the logic level forced on the pio pin. note that if the pio pin is left uncon- nected with piob set, a weak pulldown current source pulls the pio pin to v ss . piob is set to a 1 on power-up. piob is also set in sleep mode to ensure the pio pin is high-impedance in sleep mode. note: do not write piob to 0 if pspio is enabled. oc[1:0] bit field v coc (mv) v doc (mv) 0 0 -25 38 0 1 -38 50 1 0 -50 75 1 1 -75 100 table 6. coc, doc programmability sc0 bit field v sc (mv) 0 150 1 300 table 7. sc programmability bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x x sha_idle piob address 78h x sc0 oc1 oc0 x 2 0 2 -1 2 -2 msb lsb x: reserved figure 20. overcurrent and short-circuit threshold bits format downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 30 ______________________________________________________________________________________ eeprom register the eeprom register provides access control of the eeprom blocks. eeprom blocks can be locked to preventalteration of data within the block. locking a block disables write access to the block. once a block is locked, it can- not be unlocked. read access to eeprom blocks is unaffected by the lock/unlock status. eeprom register format (1fh) bit 7: eeprom copy flag (eec). a 1 in this read-only bit indicates that a copy data command is in progress. while this bit is high, writes to eeprom addresses are ignored. a 0 value in this bit indicates that data can be writtento unlocked eeprom. bit 6: eeprom lock enable (lock). when the lock bit is 0, the lock command is ignored. writing a 1 to this bit enables the lock command. after setting the lock bit, the lock command must be issued as the next command,else the lock bit is reset to 0. after the lock operation is completed, the lock bit is reset to 0. the lock bit is a volatile r/ w bit, initialized to 0 upon por. bits 5 to 2: reserved.bit 1: parameter eeprom block 1 lock flag (bl1). a 1 in this read-only bit indicates that eeprom block 1 (addresses 60h to 80h) is locked (read-only), while a 0 indicates block 1 is unlocked (read/write).bit 0: user eeprom block 0 lock flag (bl0). a 1 in this read-only bit indicates that eeprom block 0 (addresses 20h to 2fh) is locked (read-only), while a 0 indicates block 0 is unlocked (read/write). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eec lock x x x x bl1 bl0 downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 31 memory the ds2775?s2778 have a 256-byte linear memoryspace with registers for instrumentation, status, and control, as well as eeprom memory blocks to store parameters and user information. byte addresses des- ignated as ?eserved?typically return ffh when read. these bytes should not be written. several byte regis- ters are paired into 2-byte registers to store 16-bit val- ues. the msb of the 16-bit value is located at the even address and the lsb is located at the next address (odd) byte. when the msb of a 2-byte register is read, the msb and lsb are latched simultaneously and held for the duration of the read data command to prevent updates to the lsb during the read. this ensures syn- chronization between the two register bytes. for consis- tent results, always read the msb and the lsb of a 2-byte register during the same read data sequence. eeprom memory consists of nonvolatile eeprom cells overlaying volatile shadow ram. the read data and write data commands allow the 1-wire interface to directly accesse the shadow ram (figure 21). the copy data and recall data commands transfer data between the eeprom cells and the shadow ram. in order to modify the data stored in the eeprom cells, data must be written to the shadow ram and then copied to the eeprom. to verify the data stored in the eeprom cells, the eeprom data must be recalled to the shadow ram and then read from the shadow. afterissuing the copy data command, access to the eep- rom block is not available until the eeprom copy completes (see t eec in the eeprom reliability specification table). user eeprom?lock 0 a 16-byte user eeprom memory (block 0, addresses20h to 2fh) provides nonvolatile memory that is uncom- mitted to other ds2775?s2778 functions. accessing the user eeprom block does not affect the operation of the ds2775?s2778. user eeprom is lockable and, once locked, write access is not allowed. the battery pack or host system manufacturer can program lot codes, date codes, and other manufacturing or warran- ty or diagnostic information and then lock it to safe- guard the data. user eeprom can also store parameters for charging to support different size batter- ies in a host device as well as auxiliary model data such as time to full-charge estimation parameters. parameter eeprom?lock 1 model data for the cells as well as application operatingparameters are stored in the parameter eeprom mem- ory (block 1, addresses 60h to 80h). the acr (msb and lsb) and as registers are automatically saved to eeprom when the rarc result crosses 4% bound- aries (see table 8 for more information). shadow ram eeprom write recall copy read serial interface figure 21. eeprom access through shadow ram downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 32 ______________________________________________________________________________________ address (hex) description address (hex) description 60h control register 71h ae segment 3 slope register 61h accumulation bias register (ab) 72h ae segment 2 slope regi ster 62h aging capacity register msb (ac) 73h ae segment 1 slope register 63h aging capacity register lsb (ac) 74h se segment 4 slope regist er 64h charge voltage register (vchg) 75h se segment 3 slope register 65h minimum charge current register (imin) 76h se segment 2 slope regis ter 66h active-empty voltage register (vae) 77h se segment 1 slope reg ister 67h active-empty current register (iae) 78h sense-resistor gain register msb (rsgain) 68h active-empty 40 register 79h sense-resistor gain register ls b (rsgain) 69h sense resistor prime register (rsnsp) 6ah full 40 msb register 7ah sense-resistor temperature coefficient register (rstc) 6bh full 40 lsb register 7bh current offset bias register (cob) 6ch full segment 4 slope register 7ch tbp34 register 6dh full segment 3 slope register 7dh tbp23 register 6eh full segment 2 slope register 7eh tbp12 register 6fh full segment 1 slope register 7fh protector threshold register 70h ae segment 4 slope register 80h 2-wire slave address register table 8. parameter eeprom memory block address (hex) description read/write 00h protection register r/w 01h status register r/w 02h raac register msb r 03h raac register lsb r 04h rsac register msb r 05h rsac register lsb r 06h rarc register r 07h rsrc register r 08h average current register msb r 09h average current register lsb r 0ah temperature register msb r 0bh temperature register lsb r 0ch voltage register msb, v in1 - v ss r 0dh voltage register lsb, v in1 - v ss r 0eh current register msb r 0fh current register lsb r 10h accumulated current register msb r/w* 11h accumulated current register lsb r/w* 12h accumulated current register lsb - 1 r table 9. memory map downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 33 64-bit net address (rom id) each ds2775?s2778 has a unique, factory-pro-grammed rom id that is 64 bits. the first 8 bits of the net address are the product family code (3dh). the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits (see figure 22). authentication the ds2776/ds2778 have an authentication featurethat is performed using a fips 180-compliant sha-1 one-way hash algorithm on a 512-bit message block. the message block consists of a 64-bit secret, a 64-bit challenge, and 384 bits of constant data. optionally,the 64-bit net address replaces 64 of the 384 bits of constant data used in the hash operation. contact maxim for details of the message block organization. the host and the ds2776/ds2778 both calculate the result based on the mutually known secret. the result data, known as the message authentication code (mac) or message digest, is returned by the ds2776/ds2778 for comparison to the host? result. note that the secret is never transmitted on the bus and thus cannot be captured by observing bus traffic. each authentication attempt is initiated by the host system by providing a 64-bit random challenge through the write address (hex) description read/write 13h accumulated current register lsb - 2 r 14h age scalar register r/w* 15h special feature register r/w 16h full register msb r 17h full register lsb r 18h active-empty register msb r 19h active-empty register lsb r 1ah standby-empty register msb r 1bh standby-empty register lsb r 1ch voltage register msb, v in2 - v in1 r 1dh voltage register lsb, v in2 - v in1 r 1eh cycle counter register r/w* 1fh eeprom register r/w 20h to 2fh user eeprom register, lockable, block 0 r/w 30h to 5fh reserved 60h to 80h parameter eeprom register, lockable, block 1 r/w 81h to afh reserved b0h factory gain rsgain register msb r b1h factory gain rsgain register lsb r b2h to fdh reserved feh 2-wire command register w ffh reserved table 9. memory map (continued) * register value is automatically saved to eeprom during active-mode operation and recalled from eeprom on power-up. 8-bit crc 48-bit serial number 8-bit family code (3dh) msb lsb figure 22. 1-wire net address format (rom id) downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 34 ______________________________________________________________________________________ challenge command. the host then issues the computemac or compute mac with rom id command. the mac is computed per fips 180, and then returned as a 160-bit serial stream, beginning with the lsb. ds2776/ds2778 authentication commands write challenge [0ch] this command writes the 64-bit challenge to theds2776/ds2778. the lsb of the 64-bit data argument can begin immediately after the msb of the command has been completed. if more than 8 bytes are written, the final value in the challenge register is indetermi- nate. the write challenge command must be issued prior to every compute mac or compute next secret command for reliable results. compute mac without rom id [36h] this command initiates an sha-1 computation withoutincluding the rom id in the message block. because the rom id is not used, this command allows the use of a master secret and mac response independent of the rom id. the ds2776/ds2778 computes the mac in t sha after receiving the last bit of this command. after the mac computation is complete, the host mustwrite eight write-zero time slots and then issue 160 read time slots to receive the 20-byte mac. see figure 25 for command timing. compute mac with rom id [35h] this command is structured the same as the computemac without rom id, except that the rom id is includ- ed in the message block. with the rom id unique to each ds2776/ds2778 included in the mac computation, use of a unique secret in each token and a master secret in the host device is allowed. refer to application note 1099: white paper 4: glossary of 1-wire sha-1 terms for more information. see figure 25 for command timing. table 10 summarizes sha-1-related commands usedwhile authenticating a battery or peripheral device. the secret management function commands section describes four additional commands for clearing, com-puting, and locking of the secret. secret management function commands table 11 summarizes all the secret management func-tion commands. clear secret [5ah] this command sets the 64-bit secret to all 0s (00000000 0000 0000h). the host must wait for t eec for the ds2776/ds2778 to write the new secret value to eeprom. see figure 28 for command timing. compute next secret without rom id [30h] this command initiates an sha-1 computation of themac and uses a portion of the resulting mac as the next or new secret. the mac computation is performed with the current 64-bit secret and the 64-bit challenge. logical 1s are loaded in place of the rom id. the out- put mac? 64 bits are used as the new secret value. the host must allow t sha after issuing this command for the sha calculation to complete, then wait t eec for the ds2776/ds2778 to write the new secret value to eeprom. see figure 26 for command timing. compute next secret with rom id [33h] this command initiates an sha-1 computation of themac and uses a portion of the resulting mac as the next or new secret. the mac computation is performed with the current 64-bit secret, the 64-bit rom id, and the 64-bit challenge. the output mac? 64 bits are used as the new secret value. the host must allow t sha after issuing this command for the sha calculation to com-plete, then wait t eec for the ds2776/ds2778 to write command hex function write challenge 0ch writes 64-bit challenge for sha-1 processing. required prior to issuing compute mac and compute next secret commands. compute mac without rom id (and return mac for the ds2776 only) 36h computes hash of the message block with logical 1s in place of the rom id. (returns the 160-bit mac for the ds2776 only.) compute mac with rom id (and return mac for the ds2776 only) 35h computes hash of the message block including the rom id. (returns the 160-bit mac for the ds2776 only.) read rom id (ds2778 only) 39h returns the rom id (ds2778 only). read mac (ds2778 only) 3ah returns the 160-bit mac (ds2778 only). table 10. authentication function commands downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 35 the new secret value to eeprom. see figure 26 forcommand timing. lock secret [60h] this command write protects the 64-bit secret to pre-vent accidental or malicious overwrite of the secret value. the secret value stored in eeprom becomes "final." the host must wait t eec for the ds2776/ds2778 to write the lock secret bit to eeprom. see figure 28for command timing. 1-wire bus system (ds2775/ds2776 only) the 1-wire bus is a system that has a single bus masterand one or more slaves. a multidrop bus is a 1-wire bus with multiple slaves, while a single-drop bus has only one slave device. in all instances, the ds2775/ ds2776 are slave devices. the bus master is typically a microprocessor in the host system. the discussion of this bus system consists of five topics: 64-bit net address, crc generation, hardware configuration, transaction sequence, and 1-wire signaling. crc generation the ds2775/ds2776 have an 8-bit crc stored in themsb of its 64-bit net address and generates a crc during some command protocols. to ensure error-free transmission of the address, the host system can com- pute a crc value from the first 56 bits of the address and compare it to the crc from the ds2775/ds2776. the host system is responsible for verifying the crcvalue and taking action as a result. the ds2775/ ds2776 do not compare crc values and do not pre- vent a command sequence from proceeding as a result of a crc mismatch. proper use of the crc can result in a communication channel with a very high level of integrity. the crc can be generated by the host using a circuit consisting of a shift register and xor gates as shown in figure 23, or it can be generated in software using the polynomial x 8 + x 5 + x 4 + 1. additional information about the maxim 1-wire crc is available in applicationnote 27: understanding and using cyclic redundancy checks with maxim i button products . in the circuit in figure 23, the shift register bits are ini-tialized to 0. then, starting with the lsb of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial num- ber is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. during some command sequences, the ds2775/ ds2776 also generate an 8-bit crc and provide this value to the bus master to facilitate validation for the transfer of command, address, and data from the bus master to the ds2775/ds2776. the ds2775/ds2776 compute an 8-bit crc for the command and address bytes received from the bus master for the read memory, read status, and read/generate crc com- mands to confirm that these bytes have been received correctly. the crc generator on the ds2775/ds2776 is command hex function clear secret 5ah clears the 64-bit secret to 0000 0000 0000 0000h. compute next secret without rom id 30h generates new global secret. compute next secret with rom id 33h generates new unique secret. lock secret 60h sets lock bit to prevent changes to the secret. table 11. secret management function commands msb xor xor xor input lsb figure 23. 1-wire crc generation block diagram i button is a registered trademark of maxim integrated products, inc. downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 36 ______________________________________________________________________________________ also used to provide verification of error-free data trans-fer as each eeprom page is sent to the master during a read data/generate crc command and for the 8 bytes of information in the status memory field. in each case where a crc is used for data transfer val- idation, the bus master must calculate the crc value using the same polynomial function and compare the calculated value to the crc either stored in the ds2775/ds2776 net address or computed by the ds2775/ds2776. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry in the ds2775/ds2776 that prevents a command sequence from proceeding if the stored or calculated crc from the ds2775/ds2776 and the calculated crc from the host do not match. hardware configuration because the 1-wire bus has only a single line, it isimportant that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must connect to the bus with open-drain or three-state output drivers. the ds2775/ ds2776 use an open-drain output driver as part of the bidirectional interface circuitry shown in figure 24. if a bidirectional pin is not available on the bus master, separate output and input pins can be connected together. the 1-wire bus must have a pullup resistor at the bus master end. a value of between 2k and 5k is recom- mended. the idle state for the 1-wire bus is high. if, forany reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. note that if the bus is left low for more than t low0 , slave devices on the bus begin to interpret the low period as a reset pulse, effectively terminatingthe transaction. transaction sequence the protocol for accessing the ds2775/ds2776through the 1-wire port is as follows: initialization net address commands function command(s) data transfer (not all commands have data transfer) initialization all transactions of the 1-wire bus begin with an initial-ization sequence consisting of a reset pulse transmitted by the bus master, followed by a presence pulse simul- taneously transmitted by the ds2775/ds2776 and any other slaves on the bus. the presence pulse tells the bus master that one or more devices are on the bus and ready to operate. for more details, see the 1-wire signaling section. net address commands once the bus master has detected the presence of oneor more slaves, it can issue one of the net address commands described in the following sections. the name of each net address command (rom command) is followed by the 8-bit op code for that command in square brackets. read net address [33h] this command allows the bus master to read theds2775/ds2776? 1-wire net address. this command can only be used if there is a single slave on the bus. if more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). rx bus master rx = receive tx = transmit 4.7k 100na (typ) v pullup (2.0v to 5.5v) tx rx tx 100 mosfet ds2775/ds2776 1-wire port (dq) figure 24. 1-wire bus interface circuitry downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 37 match net address [55h] this command allows the bus master to specificallyaddress one ds2775/ds2776 on the 1-wire bus. only the addressed ds2775/ds2776 responds to any sub- sequent function command. all other slave devices ignore the function command and wait for a reset pulse. this command can be used with one or more slave devices on the bus. skip net address [cch] this command saves time when there is only oneds2775/ds2776 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. if more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. search net address [f0h] this command allows the bus master to use a processof elimination to identify the 1-wire net addresses of all slave devices on the bus. the search process involves the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple three-step routine on each bit location of the net address. after one complete pass through all 64 bits, the bus master knows the address of one device. the remaining devices can then be identified on additional iterations of the process. see chapter 5 in application note 937: book of i button standards for a comprehen- sive discussion of a net address search, including anactual example. function commands after successfully completing one of the net addresscommands, the bus master can access the features of the ds2775/ds2776 with any of the function commands described in the following paragraphs. the name of each function is followed by the 8-bit op code for that command in square brackets. the function commands are summarized in table 12. table 13 details the requirements for using the function commands. read data [69h, xxh] this command reads data from the ds2775/ds2776starting at memory address xxh. the lsb of the data in address xxh is available to be read immediately after the msb of the address has been entered. because the address is automatically incremented after the msb of each byte is received, the lsb of the data at address xxh + 1 is available to be read immediately after the msb of the data at address xxh. if the bus master con- tinues to read beyond address ffh, data is read start- ing at memory address 00h and the address is auto-matically incremented until a reset pulse occurs. addresses labeled reserved in the memory map con- tain undefined data values (see table 9). the readdata command can be terminated by the bus master with a reset pulse at any bit boundary. reads from eep- rom block addresses return the data in the shadow ram. a recall data command is required to transfer data from the eeprom to the shadow. see the memory section for more details. write data [6ch, xxh] this command writes data to the ds2775/ds2776 start-ing at memory address xxh. the lsb of the data to be stored at address xxh can be written immediately after the msb of the address has been entered. because the address is automatically incremented after the msb of each byte is written, the lsb to be stored at address xxh + 1 can be written immediately after the msb to be stored at address xxh. if the bus master continues to write beyond address ffh, the data starting at address 00 is overwritten. writes to read-only addresses, reserved addresses, and locked eeprom blocks are ignored. incomplete bytes are not written. writes to unlocked eeprom block addresses modify the shadow ram. a copy data command is required to transfer data from the shadow to the eeprom. see the memory section for more details. copy data [48h, xxh] this command copies the contents of the eepromshadow ram to eeprom cells for the eeprom block containing address xxh. copy data commands that address locked blocks are ignored. while the copy data command is executing, the eec bit in the eeprom register is set to 1 and writes to eeprom addresses are ignored. reads and writes to non-eeprom addresses can still occur while the copy is in progress. the copy data command takes t eec time to execute, starting on the next falling edge after the address is transmitted.see figure 27 for more information. recall data [b8h, xxh] this command recalls the contents of the eepromcells to the eeprom shadow memory for the eeprom block containing address xxh. lock [6ah, xxh] this command locks (write protects) the block of eeprom memory containing memory address xxh. the lock bit in the eeprom register must be set to 1 before the lock command is executed. to help pre- vent unintentional locks, one must issue the lock com- mand immediately after setting the lock bit (eeprom downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 38 ______________________________________________________________________________________ register, address 1fh, bit 6) to a 1. if the lock bit is 0or if setting the lock bit to 1 does not immediately precede the lock command, the lock command has no effect. the lock command is permanent; a lockedblock can never be written again. command hex description write challenge 0ch writes 64-bit challenge for sha-1 processing. required immediately prior to all compute mac and compute next secret commands. compute mac without rom id (and return mac for the ds2776 only) 36h computes hash of the message block with logical 1s in place of rom id. (returns the 160-bit mac for the ds2776 only.) compute mac with rom id (and return mac for the ds2776 only) 35h computes hash of the message block using the rom id. (returns the 160-bit mac for the ds2776 only.) clear secret 5ah clears the 64-bit secret to 0000 0000 0000 0000h. compute next secret without the rom id 30h generates new global secret. compute next secret with rom id 33h generates new unique secret. read rom id (ds2778 only) 39h returns the rom id (ds2778 only). read mac (ds2778 only) 3ah returns the 160-bit mac (ds2778 only). lock secret 60h sets lock bit to prevent changes to the secret. read data 69h, xxh reads data from memory starting at address xxh. write data 6ch, xxh writes data to memory starting at address xxh. copy data 48h, xxh copies shadow ram data to eeprom block contain ing address xxh. recall data b8h, xxh recalls eeprom block containing address xxh to r am. lock 6ah, xxh permanently locks the block of eeprom containing address xxh. reset bbh resets ds2775/ds2776 (software por). table 12. all function commands command issue memory address (bits) issue 00h before read read/write time slots write challenge write: 64 compute mac yes read: up to 160 compute next secret clear/lock secret, set/clear read data 8 read: up to 2048 write data 8 write: up to 2048 copy data 8 recall data 8 lock 8 reset table 13. guide to function command requirements downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 39 1-wire reset skip-rom command up to 160 read time slots (read 20-byte mac) presence pulse compute mac command 8 write-zero time slots wait for mac computation t sha figure 25. compute mac command 1-wire reset skip-rom command presence pulse compute next secret command wait for mac computation wait for eeprom programming t sha t eec figure 26. compute next secret command 1-wire reset skip-rom command copy data command 8 write time slots presence pulse wait for eeprom programming t eec figure 27. copy data command downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 40 ______________________________________________________________________________________ 1-wire signaling the 1-wire bus requires strict signaling protocols toensure data integrity. the four protocols used by the ds2775/ds2776 are as follows: the initialization sequence (reset pulse followed by presence pulse), write-zero, write-one, and read data. the bus master initiates all these types of signaling except the pres- ence pulse. figure 29 shows the initialization sequence required tobegin any communication with the ds2775/ds2776. a presence pulse following a reset pulse indicates that the ds2775/ds2776 are ready to accept a net address command. the bus master transmits (tx) a reset pulse for t rstl . the bus master then releases the line and goes into receive mode (rx). the 1-wire bus line isthen pulled high by the pullup resistor. after detecting the rising edge on the dq pin, the ds2775/ds2776 wait for t pdh and then transmit the presence pulse for t pdl . 1-wire reset skip-rom command clear/lock secret command or set/clear overdrive command presence pulse wait for eeprom copy time t eec figure 28. clear/lock secret, set/clear overdrive commands resistor pullup bus master active low line type legend: dq ds2775/ds2776 active low pk+pk- t rstl t rsth t pdl t pdh figure 29. 1-wire initialization sequence downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 41 write time slots a write time slot is initiated when the bus master pullsthe 1-wire bus from a logic-high (inactive) level to a logic-low level. there are two types of write time slots: write-one and write-zero. all write time slots must be t slot in duration with a 1? minimum recovery time, t rec , between cycles. the ds2775/ds2776 sample the 1-wire bus line between t low1_max and t low0_min after the line falls. if the line is high when sampled, awrite-one occurs. if the line is low when sampled, a write-zero occurs. figure 30 illustrates the sample win- dow. for the bus master to generate a write-one time slot, the bus line must be pulled low and then released, allowing the line to be pulled high less than t rdv after the start of the write time slot. for the host to generate awrite-zero time slot, the bus line must be pulled low and held low for the duration of the write time slot. read time slots a read time slot is initiated when the bus master pulls the1-wire bus line from a logic-high level to a logic-low level. the bus master must keep the bus line low for at least 1? and then release it to allow the ds2775/ ds2776 to present valid data. the bus master can then sample the data t rdv from the start of the read time slot. by the end of the read time slot, the ds2775/ds2776release the bus line and allow it to be pulled high by the external pullup resistor. all read time slots must be t slot in duration with a 1? minimum recovery time, t rec , between cycles. see figure 30 and the timing specifica-tions in the electrical characteristics: 1-wire interface, standard/overdrive tables for more information. 2-wire bus system the 2-wire bus system supports operation as a slave-only device in a single or multislave and single or multi- master system. up to 128 slave devices can share the bus by uniquely setting the 7-bit slave address. the 2-wire interface consists of a serial data line (sda) and serial clock line (scl). sda and scl provide bidirec- tional communication between the ds2777/ds2778 slave device and a master device at speeds up to 400khz. the ds2777/ds2778? sda pin operates bidi- rectionally, that is, when the ds2777/ds2778 receive data, sda operates as an input, and when the ds2777/ds2778 return data, sda operates as an open- drain output with the host system providing a resistive pullup. the ds2777/ds2778 always operate as a slave device, receiving and transmitting data under the con- trol of a master device. the master initiates all transac-tions on the bus and generates the scl signal as well as the start and stop bits which begin and end each transaction. bit transfer one data bit is transferred during each scl clock cyclewith the cycle defined by scl transitioning low-to-high and then high-to-low. the sda logic level must remain stable during the high period of the scl clock pulse. any change in sda when scl is high is interpreted as a start (s) or stop (p) control signal. bus idle the bus is defined to be idle, or not busy, when nomaster device has control. both sda and scl remain high when the bus is idle. the stop condition is the proper method to return the bus to the idle state. start and stop conditions the master initiates transactions with a start condi-tion by forcing a high-to-low transition on sda while scl is high. the master terminates a transaction with a stop condition, a low-to-high transition on sda while scl is high. a repeated start condition (sr) can be used in place of a stop then start sequence to ter- minate one transaction and begin another without returning the bus to the idle state. in multimaster sys- tems, a repeated start allows the master to retain control of the bus. the start and stop conditions are the only bus activities in which the sda transitions when scl is high. acknowledge bits each byte of a data transfer is acknowledged with anacknowledge bit (a) or a not acknowledge bit (n). both the master and the ds2777/ds2778 slave generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (9th pulse) and keep it low until scl returns low. to gener- ate a not acknowledge (also called nack), the receiver releases sda before the rising edge of the acknowl- edge-related clock pulse and leaves sda high until scl returns low. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication. downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 42 ______________________________________________________________________________________ resistor pullup bus master active low line type legend: slave active low both bus master andslave active low t slot t low0 t rec t rec t low1 > 1 s > 1 s t slot t slot t rdv t rdv 30 s 15 s 3 s 2 s 15 s 2 s 15 s 2 s 1 s t slot v pullup write-zero slot write-one slot read-zero slot read-one slot gnd v pullup gnd master sample window master sample window mode: standard mode: overdrive standard overdrive device sample window min typ max device sample window min typ max 15 s 30 s 15 s 3 s 2 s 1 s 15 s figure 30. 1-wire write and read time slots downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 43 data order a byte of data consists of 8 bits ordered msb first. thelsb of each byte is followed by the acknowledge bit. the ds2777/ds2778 registers composed of multibyte values are ordered msb first. the msb of multibyte reg- isters is stored on even data memory addresses. slave address a bus master initiates communication with a slavedevice by issuing a start condition followed by a slave address (saddr) and the read/write (r/ w ) bit. when the bus is idle, the ds2777/ds2778 continuouslymonitor for a start condition followed by its slave address. when the ds2777/ds2778 receive a slave address that matches the value in its programmable slave address register, they respond with an acknowl- edge bit during the clock period following the r/ w bit. the 7-bit programmable slave address register is fac-tory programmed to 1011001. the slave address can be reprogrammed. see the programmable slave address section for details. programmable slave address the 2-wire slave address of the ds2777/ds2778 isstored in the parameter eeprom block, address 80h. programming the slave address requires a write to 80h with the desired slave address. the new slave address value is effective following the write to 80h and must be used to address the ds2777/ds2778 on subsequent bus transactions. the slave address value is not stored to eeprom until a copy eeprom block 1 command is executed. prior to executing the copy data command, power cycling the ds2777/ds2778 restores the original slave address value. the data format of the slave address value in address 80h is shown in the slave address format (80h) section. read/write bit the r/ w bit following the slave address determines the data direction of subsequent bytes in the transfer. r/ w = 0 selects a write transaction, with the subsequentbytes being written by the master to the slave. r/ w = 1 selects a read transaction, with the subsequent bytesbeing read from the slave by the master. bus timing the ds2777/ds2778 are compatible with any bus tim-ing up to 400khz. no special configuration is required to operate at any speed. 2-wire command protocols the command protocols involve several transaction for-mats. the simplest format consists of the master writing the start bit, slave address, r/ w bit, and then moni- toring the acknowledge bit for presence of theds2777/ds2778. more complex formats such as the write data, read data, and function command proto- cols write data, read data, and execute device-specific operations. all bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. each function command definition outlines the required transaction format. table 14 applies to the transaction formats. basic transaction formats write: s saddr w a maddr a data0 a p a write transaction transfers one or more data bytes tothe ds2777/ds2778. the data transfer begins at the memory address supplied in the maddr byte. control of the sda signal is retained by the master throughout the transaction, except for the acknowledge cycles. a read transaction transfers one or more bytes from the ds2777/ds2778. read transactions are composed oftwo parts with a write portion followed by a read portion and are, therefore, inherently longer than a write trans- action. the write portion communicates the starting point for the read operation. the read portion follows immediately, beginning with a repeated start, and slave address with r/ w set to a 1. control of sda is read: s saddr w a maddr a sr saddr r a data0 n p write portion read portion bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a6 a5 a4 a3 a2 a1 a0 x slave address format (80h) bits 7 to 1: slave address (a[6:0]). a[6:0] contains the 7-bit slave address of the ds2777/ds2778. the factory default is 1011001b.bit 0: reserved. downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication 44 ______________________________________________________________________________________ key description key description s start bit sr repeated start saddr slave address (7-bit) w r/ w bit = 0 fcmd function command byte r r/ w bit = 1 maddr memory address byte p stop bit data data byte written by master data data byte returned by sla ve a acknowledge bit (master) a acknowledge bit (slave) n not acknowledge (master) n not acknowledge (slave) table 14. 2-wire protocol keyassumed by the ds2777/ds2778 beginning with the slave address acknowledge cycle. control of the sda signal is retained by the ds2777/ds2778 throughout the transaction, except for the acknowledge cycles. the master indicates the end of a read transaction by responding to the last byte it requires with a no acknowledge. this signals the ds2777/ds2778 that control of sda is to remain with the master following the acknowledge clock. write-data protocol the write-data protocol is used to write to register andshadow ram data to the ds2777/ds2778 starting at memory address maddr. data0 represents the data written to maddr, data1 represents the data written to maddr + 1 and datan represents the last data byte, written to maddr + n. the master indicates the end of a write transaction by sending a stop or repeated start after receiving the last acknowledge bit. s saddr w a maddr a data0 a data1 a ?datan a p the msb of the data to be stored at address maddrcan be written immediately after the maddr byte is acknowledged. because the address is automatically incremented after the lsb of each byte is received by the ds2777/ds2778, the msb of the data at address maddr + 1 is written immediately after the acknowl- edgement of the data at address maddr. if the bus master continues an autoincremented write transaction beyond address 4fh, the ds2777/ds2778 ignore the data. data is also ignored on writes to read-only addresses and reserved addresses, locked eeprom blocks, as well as a write that auto-increments to the function command register (address feh). incomplete bytes and bytes that are not acknowledged by the ds2777/ds2778 are not written to memory. as noted in the memory section, writes to unlocked eeprom blocks modify the shadow ram only. read-data protocol the read-data protocol is used to read register andshadow ram data from the ds2777/ds2778 starting at a memory address specified by maddr. data0 repre- sents the data byte in memory location maddr, data1 represents the data from maddr + 1, and datan repre- sents the last byte read by the master. s saddr w a maddr a sr saddr r a data0 a data1 a ?datan n p data is returned beginning with the msb of the data inmaddr. because the address is automatically incre- mented after the lsb of each byte is returned, the msb of the data at address maddr + 1 is available to the host immediately after the acknowledgement of the data at address maddr. if the bus master continues to read beyond address ffh, the ds2777/ds2778 output data values of ffh. addresses labeled reserved in the memory map return undefined data. the bus master terminates the read transaction at any byte boundaryby issuing a not acknowledge followed by a stop or repeated start. function command protocol the function command protocol executes a device-specific operation by writing one of the function com- mand values (fcmd) to memory address feh. table 15 lists the ds2777/ds2778 fcmd values and describes the actions taken by each. a 1-byte write protocol is used to transmit the function command, with the maddr set to feh and the data byte set to the desired fcmd value. additional data bytes are ignored. data read from memory address feh is undefined. s saddr w a maddr = 0feh a fcmd a p downloaded from: http:///
ds2775/ds2776/ds2777/ds2778 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ______________________________________________________________________________________ 45 function command target eeprom block fcmd value description 0 42h copy data 1 44h this command copies the shadow ram to the target eeprom block. copy data commands that target locked blocks are ignored. while the copy data command is executing, the eec bit in the eeprom register is set to 1, and writ e data commands with maddr set to any address within the target block are ignored . read data and write data commands with maddr set outside the target block are processed wh ile the copy is in progress. the copy data command execution time, t eec , is 2ms typical and starts after the fcmd byte is acknowledged. subsequent copy or lock commands must be delayed until the eeprom programming cycle comp letes. 0 b2h recall data 1 b4h this command recalls the contents of the targeted eeprom block to it s shadow ram. 0 63h lock 1 66h this command locks (write protects) the targeted eeprom block. the lock bit in the eeprom register must be set to 1 before the lock command i s executed. if the lock bit is 0, the lock command has no effect. the lock command is permanent; a locked block can never be written again. the lock command execution time, t eec , is 2ms typical and starts after the fcmd byte is acknowledged. sub sequent copy or lock commands must be delayed until the eeprom program ming cycle completes. read rom id 39h this command initiates a read of the unique 64-bit rom id. after the read rom id command is sent, the rom id can be read with the following sequence: s saddr r data0 a data1 a ... data7 n p. table 15. function commands selector guide part interface sha-1 ds2775 g+ 1-wire no ds2775g+t&r 1-wire no ds2776 g+ 1-wire yes ds2776g+t&r 1-wire yes ds2777 g+ 2-wire no ds2777g+t&r 2-wire no ds2778 g+ 2-wire yes ds2778g+t&r 2-wire yes + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. package type package code outline no. land pattern no. 14 tdfn-ep t1435n+1 21-0253 90-0246 package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
revision history revision number revision date description pages changed 0 10/08 initial release 1 3/09 corrected values in the vov register programmabilit table (table 5) 27 2 7/09 corrected the 2-wire slave address default value to 1011001 42 3 5/10 clarified esd sensitivity to avoid confusion 2, 7, 11, 13, 24, 25, 45 4 6/11 updated the ds2775/ds2776 tpical application circuit and ds2777/ds2778 tpical application circuit ; corrected the product family code from 32h to 3dh in the 64-bit net address (rom id) section and figure 22 10, 33 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 46 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. 2-cell, stand-alone, li+ fuel-gauge ic with protector and optional sha-1 authentication ds2775/ds2776/ds2777/ds2778 downloaded from: http:///

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